After FinFET: where the transistor goes next
For almost twenty years, the FinFET has been the transistor that enabled every major logic node.
Introduced by Intel at 22nm in 2011, it replaced the planar MOSFET with a vertical silicon fin, allowing the gate to control the channel from three sides instead of one. The result was much better electrostatic control, lower leakage current and higher drive capability. That architecture successfully scaled from 22nm down to today’s 5nm-class technologies.
Eventually, though, scaling reached its limits.
As gate lengths approach 5nm and below, short-channel effects become increasingly difficult to suppress. The fin cannot simply become narrower forever without degrading electrostatic control, increasing leakage and hurting variability. At that point, improving lithography alone is no longer enough; the transistor architecture itself has to change.
Gate-All-Around: the logical evolution
The industry’s answer is the Gate-All-Around (GAA) transistor.
Instead of wrapping around three sides of the channel, the gate completely surrounds it. The silicon fin disappears and is replaced by one or more suspended horizontal nanosheets enclosed by the gate stack. With the gate controlling all four sides of the channel, electrostatics improve significantly, allowing further scaling while keeping leakage under control.
Samsung was the first company to bring GAA into production with its 3nm MBCFET technology in 2022. The initial ramp was challenging, but the architecture proved viable. Intel and TSMC are following with their 2nm-class technologies.
Although all three foundries use the same basic concept, their implementations differ. Samsung’s MBCFET allows designers to tune both nanosheet width and the number of stacked sheets, offering additional flexibility to optimize either performance or power efficiency. TSMC has instead taken a more conservative approach, focusing on manufacturing maturity and yield before introducing additional innovations such as backside power delivery.
More importantly, GAA removes one of the biggest limitations of the FinFET: it opens the door to true three-dimensional transistor scaling.
Forksheet and CFET
Once nanosheet GAA is established, the roadmap naturally moves toward two new architectures: Forksheet and CFET.
Forksheet keeps the horizontal nanosheet structure but reduces the spacing between NMOS and PMOS devices by separating them with a thin dielectric wall. The concept increases transistor density without completely redesigning the device architecture. IBM has been one of the main contributors in this area, demonstrating very compact layouts while maintaining design flexibility through tunable transistor spacing.
The next step is considerably more ambitious.
Rather than placing NMOS and PMOS side by side, CFET (Complementary FET) stacks them vertically. The potential density improvement is significant because two neighboring transistors effectively become one vertical structure. Intel, Samsung and TSMC have all demonstrated research prototypes, although high-volume manufacturing remains several years away.
Samsung’s latest result
One of the most interesting developments came during the VLSI Symposium earlier this month.
Samsung presented what it calls a 3D Stacked FET with triple-stacked nanosheet channels fabricated at a 42nm gate pitch. The work received one of the highest review scores among more than one thousand submitted papers and was recognized with a Best Paper award.
This is not yet commercial CFET, but it is an important milestone. Demonstrating vertical transistor integration at realistic geometries suggests that the remaining challenges are increasingly becoming manufacturing problems rather than fundamental device limitations.
IBM’s nanostack
Only a few days later, IBM announced what it describes as the world’s first sub-1nm transistor technology.
The new “nanostack” architecture integrates nearly 100 billion transistors on a chip roughly the size of a fingernail, around twice the density of IBM’s previous 2nm demonstrator. According to IBM, the technology could eventually deliver around 50% higher performance or 70% lower power consumption than its earlier design.
The interesting part is not the marketing name but the direction.
Nanostack builds directly on the nanosheet GAA architecture that IBM first demonstrated in 2017. Instead of continuing aggressive lateral scaling, IBM is pushing transistor density through vertical integration. In other words, future scaling increasingly happens in the third dimension.
That said, it is important to keep expectations realistic. IBM is not a commercial foundry, and this is still a research vehicle rather than a manufacturable technology. The company’s 2nm demonstration dates back to 2021 and is only now approaching commercial deployment through manufacturing partners. Sub-1nm therefore represents a direction of travel rather than an imminent production node.
Beyond silicon
There is another issue that transistor architecture alone cannot solve.
As nanosheet thickness approaches only a few nanometers, silicon itself begins to lose performance. Carrier mobility decreases because quantum confinement effects become increasingly important, meaning that further scaling is limited by the material rather than by the device geometry.
For this reason, much of today’s research focuses on two-dimensional semiconductors, particularly transition metal dichalcogenides such as molybdenum disulfide (MoS₂).
Since these materials are naturally only one atomic layer thick, they offer much better electrostatic control at extremely small dimensions and could enable gate lengths well below those achievable with silicon. According to the IRDS roadmap, they may become relevant for advanced logic sometime during the late 2030s.
However, major manufacturing challenges remain. Uniform wafer-scale growth, low-resistance contacts and defect control all still require substantial progress before these materials become commercially viable.
The bigger picture
Looking at today’s roadmap, the direction is becoming increasingly clear.
Gate-All-Around is now entering mainstream production. Forksheet is expected to provide the next density improvement without radically changing today’s design methodology, while CFET introduces true vertical CMOS integration. IBM’s nanostack points even further in the same direction, suggesting that future transistor scaling will rely far more on stacking than on shrinking individual devices laterally.
For circuit designers, this is more than an academic exercise. The standard cells, power delivery schemes and EDA methodologies being developed today for nanosheet GAA will form the basis for future CFET technologies. Understanding these architectures now means understanding the next generation of logic design.
The semiconductor industry has already reinvented the transistor several times. Everything suggests that the next reinvention is already underway.
